1. Field of the Invention
The present invention relates to a design support system which conducts circuit simulation in circuit designing and, more particularly, to a design support system having a function of editing and managing circuit designing data for use in circuit simulation.
2. Description of the Related Art
In circuit simulation using a design support system implemented by a computer system, required circuit designing data is obtained by repeating a predetermined procedure including inputting processing of circuit data to be processed, simulation processing and determination processing for determining whether a simulation result meets design specification.
FIG. 10 is a flow chart showing a circuit simulation executing procedure by a conventional design support system. Operation of the conventional circuit simulation will be described with reference to FIG. 10. First, data for simulation is read from a data file (Step 1001) to execute simulation (Step 1002). Then, determination is made whether the simulation result is good or not (Step 1003) and when the simulation result meets circuit specification, all the processing of the circuit simulation is completed. On the contrary, when the simulation result fails to meet the circuit specification, necessary editing and correction is given to the input data (Step 1004) to again execute the simulation (Step 1002). Hereinafter, the circuit simulation is repeatedly conducted until a simulation result meets the circuit specification.
Efficiency of circuit designing has been conventionally improved through automatization of the above-described series of circuit simulation procedures. Conventional art of this kind is recited, for example, in Japanese Patent Laying open (Kokai) No. Heisei 5-40799, entitled "Data Processor". FIG. 11 is a block diagram showing structure of the data processor recited in the literature.
In FIG. 11, an input data editing unit 1102 edits a parameter value of input data 1101 for simulation to take the value as input data. A simulation execution control unit 1104 produces control data for executing simulation as many times as the number of variations of parameters based on the edited input data. A simulation executing unit 1105 executes a designated number of times of simulation based on the control data produced by the simulation execution control unit 1104. A resultant data extracting unit 1110 extracts necessary resultant data from the resultant data (1)-(n) obtained by the simulation by the simulation executing unit 1105. A determination unit 1111 determines whether the resultant data extracted by the resultant data extracting unit 1110 satisfies predetermined conditions or not. A characteristic diagram drawing and displaying unit 1113 draws a characteristic diagram of a circuit based on a determination result obtained by the determination unit 1111 and displays the diagram on a display 1114, as well as causing a characteristic diagram outputting unit 1116 to output a characteristic diagram 1117. A result displaying unit 1115 displays the resultant data extracted by the resultant data extracting unit 1110 on the display 1114.
Other than the automatization of a series of simulation procedures as mentioned above, the above-described conventional design support system can adopt a method of conducting simulation processing and input data editing processing based on user's own decision. Possible technique of conducting processing according to user's decision is employing a circuit simulator (design support system) as an interpreter.
FIG. 12 is a block diagram showing structure of a conventional circuit simulator formed as an interpreter. In FIG. 12, first, according to an input data reading command applied through an input device 1201, data stored in a data file 1202 is accepted as internal data 1208 of an interpreter 1207. Then, according to the command applied from the input device 1201 to the interpreter 1207, a simulation executing unit 1203, a result displaying unit 1204 and an editing/displaying unit 1205 execute simulation processing, simulation result displaying processing and input data editing processing, respectively, using the internal data 1208 of the interpreter 1207.
As described in the foregoing, in a circuit simulator with an input data editing function, data management is extremely important for the purpose of efficiently conducting input data editing processing. In particular, as semiconductor integrated circuits have been increased in scale as objects of circuit configuration, the importance of data management is enhanced. Therefore, various data management techniques have been conventionally proposed. Conventional techniques related to the data management of this kind are, for example, those disclosed in Japanese Patent Laying Open (Kokai) No. Heisei 4-107682, entitled "Logical Simulator" and Japanese Patent Laying Open (Kokai) No. Heisei 3-20872, entitled "Element-Based Management Method in Circuit Synthesis System". In these conventional techniques, data management is conducted in hierarchical structure.
The design support system disclosed in Japanese Patent Laying Open (Kokai) No. Heisei 4-107682 conducts hierarchical management simulation with respect to a party to be connected therewith to reduce processing time for model generation and correction, thereby enabling simulation of a large capacity model. FIG. 13 is a block diagram showing a flow of simulation processing by the design support system recited in this literature.
The design support system shown in FIG. 13 includes a model generating unit 1301 for generating a logic circuit of a model and a simulation executing unit 1305 for executing simulation using a model generated by the model generating unit 1301. The model generating unit 1301 includes a model layering unit 1302 for checking a model structure and converting it into a layered model, a model compressing unit 1303 for compressing layered data, and a connection conversion registering unit 1304 for defining connection conversion rules for the data compressed by the model compressing unit 1303.
FIGS. 14 (A), (B) and (C) are diagrams showing data structure of a model generated at the model generating unit 1301. With reference to these figures, processing by the model generating unit 1301 will be described. First, the model layering unit 1302 checks model structure to layer the data of the model as shown in FIG. 14(A). Then, the model compressing unit 1303 conducts compression processing with respect to the data layered by the model layering unit 1302 by putting equivalent models together on a basis of a layered function as shown in FIG. 14(B). The connection conversion registering unit 1304, as shown in FIG. 14(C), registers connection management information which defines conversion rules for compressed data to maintain a connection relationship. For thus generated model, the simulation executing unit 1305 executes simulation.
The design support system disclosed in Japanese Patent Laying open (Kokai) No. Heisei 3-20872, based on a tree structure position indicated by a first pointer and real circuit element information indicated by a second pointer, manages correspondence of a real circuit element in a circuit being implemented to a functional block in a functional diagram, thereby reducing a required memory capacity. FIG. 15 is a block diagram showing the principle of the data management method by the design support system recited in this literature.
The design support system shown in FIG. 15 includes a hierarchical structure storing unit 1501 for storing a hierarchical structure in a functional diagram as a tree structure, with each element having a first pointer and a second pointer, and a real circuit element information storing unit 1502 for storing information related to an actual circuit element on a functional block basis. Information included in the real circuit element information storing unit 1502 are, for example, page, position and functional block name of an element and a hierarchical block.
When adapted, for example, to a circuit simulator such as a SPICE, the foregoing conventional techniques will be effective in expressing a link between upper and lower hierarchies among blocks and finding from which block a circuit element is generated at the time of development of the hierarchy. In order to find a linkage among circuit elements in the same hierarchy, however, the procedure is necessary of ascending the hierarchy from the circuit element level up to the block level and then descending down to the circuit element level. With a circuit simulator which frequently deals with circuit elements in the same hierarchy, partial editing is impossible.
Another shortcoming is that at the time of manually editing input data, circuit scale will be increased to exceed a capacity which can be dealt by a common editing means, disabling editing processing, or even if editing processing is executable, dealing a large volume of editing data requires enormous time to cause correction errors more frequently.
On the other hand, the conventional art disclosed in Japanese Patent Laying Open (Kokai) No. Heisei 5-40799 automatically edits a varying parameter value to vary the parameter, thereby conducting simulation. Inputting data according to prescribed parameter varying conditions is therefore possible but partial editing of parameters is impossible.
It is also possible to make varying parameters into variables and vary only the variables. With this technique, however, as the circuit is increased in scale, the number of variables is accordingly increased to make seizing of variables of variation difficult.
Moreover, with a circuit simulator employed as an interpreter, since an interpreter in general employing text input manages internal data as character-string data, data input/output processing efficiency is improved, while with respect to such peculiar data as input data for simulation, classification of circuit blocks and description data is difficult and partial editing is accordingly difficult.